Return to site

Verilog how to create linear feedback shift register

broken image
broken image

That produces WS bits at a time–rather than just one. That our resulting implementation actually works. We’ll also do one more: let’s formally prove at the end of our development, Getting these extra bits, and then discuss the code that implements this. We’ll start with describing how we’ll go about So the only thing that needs to change today is the number of outputsīits we need to generate. To drive an output serializer at high speed.Īnd see if we can modify it to produce more than one output per clock Generated one bit per clock, and I will need several bits per clock in order Indeed, if all goes well I should be able to apply Shannon’s Capacity Representing my channel, and examine the waveform at the other end to getĪn estimate of the channel throughput and I’ll then receive the bits at the other end of a My intention was to use a setup like Fig 1 to the right. However, neither of these developments have solved the problem I had

broken image